`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/05/31 11:18:00
// Design Name: 
// Module Name: decoder38_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module decoder38_tb;
reg a,b,c;
wire y0,y1,y2,y3,y4,y5,y6,y7;
decoder38 u1(a,b,c,y0,y1,y2,y3,y4,y5,y6,y7);
initial begin
a=0;b=0;c=0;
end
always #10 {a,b,c}={a,b,c}+1;
endmodule
